1. Field of the Invention
The present invention relates to a level converting circuit. To put it in more detail, the present invention relates to improvement of a circuit for converting a logic-signal level, which is referred to hereafter as a MOS level, of a TTL (Transistor-Transistor Logic) circuit into a logic signal at an ECL (Emitter-Coupled Logic) level.
2. Description of the Related Art
In recent years, efforts are made to put enhanced performance and to embed more functions into semi-conductor integrated circuits which are also known as LSI devices. For example, there is a demand for electronic portable equipment driven by a battery that meets requirements such as that the equipment be small in size, have a light weight, be operatable using a low driving voltage and consume only little power. In addition, it is also required that a test cable employed in an LSI tester for testing such an LSI device be capable of transmitting a logic signal at an ECL level in order to increase the speed of the test operation. According to the conventional technology, however, a level converting circuit to which the present invention relates is a combination of an ECL output circuit comprising bipolar transistors and a level converter comprising field-effect transistors.
Therefore, when integrating such a level converting circuit into a single chip made of a semiconductor substrate, its manufacturing process becomes complicated, giving rise to a high production cost. Much like the ECL output circuit, a level converter can also be designed using bipolar transistors to simplify the manufacturing process. In an LSI device having bipolar transistors as its main components, however, power consumption can hardly be reduced.
Here, a technology embraced by a level converting circuit provided by the present invention is described. A configuration diagram of a level converting circuit embracing the technology provided by the present invention is shown in FIG. 1. FIG. 2 is a diagram showing operation wave forms of the level converting circuit.
In general, the level converting circuit comprises a level converter 1 driven by a -5[V] power-supply system and an ECL output circuit 2 driven by a -5.2[V] power-supply system. As shown in FIG. 1, the level converter 1 and the ECL output circuit 2 are connected to each other. A termination element 3 is connected to an output unit OUT of the level converting circuit.
The level converter 1 driven by the -5[V] power-supply system comprises field-effect transistors. The level converter 1 reduces a logic signal at a MOS level into a logic amplitude voltage for the ECL output circuit 2 which is driven by the 3[V] power-supply system. Receiving the logic input signal at a MOS level with a reduced voltage amplitude, e.g., an uninverted logic signal D and its associated inverted logic signal D, the ECL output circuit 2 generates a logic output signal, for example, an uninverted logic signal Q and its associated inverted logic signal Q.
The ECL output circuit 2 comprises a differential amplifier, a first bias component R11, a second bias component R12, a third bias component R13 a fourth bias component R14 and an output circuit. The differential amplifier further comprises a first bipolar transistor Q1, a second bipolar transistor Q2 and a third bipolar transistor Q3 whereas the output circuit comprises a fourth bipolar transistor Q4 and a fifth bipolar transistor Q5.
With the level converting circuit described above, the ECL output circuit 2 driven by the -5.2[V] power-supply system can output, for example, a `H`-level (high-level) voltage VoH of the order of -0.9[V] and an `L`-level (low-level) voltage VoL of the order of -1.7[V] to a transmission line having a characteristic impedance of 50 ohms without changing the -5.2[V] signal logic with a reduced voltage amplitude of the -5[V] power-supply system as shown in FIG. 2.